1. Field of the Invention
This invention relates to a plasma display panel, and more particularly to a plasma display panel that is capable of generating a sinusoidal initialization waveform and a driving method thereof.
2. Description of the Related Art
Generally, a plasma display panel (PDP) is a display device utilizing a visible light emitted from a phosphor layer when an ultraviolet ray generated by a gas discharge excites the phosphor layer. The PDP has an advantage in that it has a thinner thickness and a lighter weight in comparison to an existing cathode ray tube (CRT) and is capable of realizing a high resolution and a large-scale screen. The PDP includes a plurality of discharge cells arranged in a matrix pattern, each of which makes one pixel of a field.
FIG. 1 is a perspective view showing a discharge cell structure of a conventional three-electrode, alternating current (AC) surface-discharge PDP.
Referring to FIG. 1, a discharge cell of the conventional three-electrode, AC surface-discharge PDP includes a first electrode 12Y and a second electrode 12Z provided on an upper substrate 10, and an address electrode 20X provided on a lower substrate 18.
On the upper substrate 10 provided with the first electrode 12Y and the second electrode 12Z in parallel, an upper dielectric layer 14 and a protective layer 16 are disposed. Wall charges generated upon plasma discharge are accumulated into the upper dielectric layer 14. The protective layer 16 prevents a damage of the upper dielectric layer 14 caused by a sputtering during the plasma discharge and improves the emission efficiency of secondary electrons. This protective layer 16 is usually made from magnesium oxide (MgO).
A lower dielectric layer 22 and barrier ribs 24 are formed on the lower substrate 18 provided with the address electrode 20X. The surfaces of the lower dielectric layer 22 and the barrier rib 24 are coated with a phosphor layer 26. The address electrode 20X is formed in a direction crossing the first electrode 12Y and the second electrode 12Z.
The barrier rib 24 is formed in parallel to the address electrode 20X to prevent an ultraviolet ray and a visible light generated by a discharge from being leaked to the adjacent discharge cells. The phosphor layer 26 is excited by an ultraviolet ray generated during the plasma discharge to generate any one of red, green and blue visible light rays. An inactive gas for a gas discharge is injected into a discharge space defined between the upper and lower substrate 10 and 18 and the barrier rib 24.
FIG. 2 shows a driving apparatus for the conventional three-electrode, AC surface-discharge type PDP.
Referring to FIG. 2, the driving apparatus for the conventional three-electrode, AC surface-discharge type PDP includes a PDP 30 having m×n discharge cells 1 arranged in a matrix type in such a manner to be connected to first electrode lines Y1 to Ym, second electrode lines Z1 to Zm and address electrode lines X1 to Xn, a first sustain driver 32 for driving the first electrode lines Y1 to Ym, a second sustain driver 34 for driving the second electrode lines Z1 to Zm, and first and second address drivers 36A and 36B for proving a divisional driving of odd-numbered address electrode lines X1, X3, . . . , Xn−3, Xn−1 and even-numbered address electrode lines X2, X4, . . . , Xn−2, Xn.
The first sustain driver 32 sequentially applies a scan pulse to the first electrode lines Y1 to Ym. Further, the first sustain driver 32 commonly applies a sustain pulse to the first electrode lines Y1 to Ym. The second sustain driver 34 applies a sustain pulse to all the second electrode lines Z1 to Zm. The first and second address drivers 36A and 36B supplies the address electrode lines X1 to Xn with an image data in such a manner to be synchronized with the scan pulse. The first address driver 36A supplies the odd-numbered address electrodes X1, X3, . . . , Xn−3, Xn−1 with an image data while the second address driver 36B supplies the even-numbered address electrode lines X2, X4, . . . , Xn−2, Xn with an image data.
Such a three-electrode AC surface-discharge PDP drives one frame, which is divided into various sub-fields having a different discharge frequency, so as to express gray levels of a picture. Each sub-field is again divided into an initialization period for uniformly causing a discharge, an address period for selecting the discharge cell and a sustain period for realizing the gray levels depending on the discharge frequency. For instance, when it is intended to display a picture of 256gray levels, a frame interval equal to 1/60 second (i.e. 16.67 msec) is divided into 8 sub-fields SF1 to SF8. Each of the 8 sub-fields SF1 to SF8 is divided into an address period and a sustain period. The initialization period and the address period of each sub-field are equal every sub-field, whereas the sustain period are increased at a ratio of 2n(wherein n=0, 1, 2, 3, 4, 5, 6 and 7) at each sub-field.
In the mean time, the PDP is largely classified into a selective writing system and a selective erasing system depending upon an emission type of a discharge cell selected by an address discharge.
The selective writing system turns on discharge cells selected in the address period after turning off the entire field in the initialization period. Subsequently, it makes a sustain discharge of discharge cells selected by the address discharge in the sustain period to thereby display a picture.
On the other hand, the selective erasing system turn off discharge cells selected in the address period after turning on the entire field in the initialization period. Subsequently, it makes a sustain discharge of discharge cells unselected by the address discharge in the sustain period.
FIG. 4 illustrates a driving waveform applied to each electrode line of the PDP for each sub-field in the conventional selective writing driving system.
Referring to FIG. 4, one sub-field is divided into an initialization period for initializing the entire field, an address period for writing a data while scanning the entire field on a line-sequence basis, and a sustain period for keeping light-emission states of cells into which a data has been written.
First, in the initialization period, an initialization waveform RP is applied to the first electrode lines Y1 to Ym. If the initialization waveform RP is applied to the first electrode lines Y1 to Ym, then an initialization discharge is generated between the first electrode lines Y1 to Ym and the second electrode lines Z1 to Zm to initialize a discharge cell. At this time, a misfiring prevention pulse is applied to the address electrode lines X1 to Xn.
In the address period, a scan pulse −Vs is sequentially applied to the first electrode lines Y1 to Ym. A data pulse Vd synchronized with the scan pulse −Vs is applied to the address electrode lines X1 to Xn. At this time, an address discharge occurs at the discharge cells to which the data pulse Vd and the scan pulse −Vs.
In the sustain period, first and second sustain pulses SUSPy and SUSPz are applied to the first electrode lines Y1 to Ym and the second electrode lines Z1 to Zm, respectively.
Meanwhile, a rectangular initialization waveform shown in FIG. 4 causes a strong initialization discharge at the discharge cells to lead the discharge cells into a certain state. However, if a strong initialization discharge occurs at the discharge cells, then the corresponding light is generated to cause contrast deterioration. In order to compensate for such a drawback, there has been a ramp waveform as shown in FIG. 5.
FIG. 5 illustrates a driving waveform applied to each electrode line of the conventional PDP.
Referring to FIG. 5, a ramp waveform R with a rising slope Ru and a falling slope Rd is applied to the first electrode lines Y1 to Ym in the initialization period. In the rising interval Ru of the ramp waveform R, a slowly rising voltage is applied to the discharge cells. If a voltage rises slowly within the discharge cell, then a current flowing through a discharge gas is limited. Thus, a wall charge is formed within the discharge cell by a number of dark discharges. On the other hand, in a falling interval Rd of the ramp waveform R, a slowly falling voltage is applied to the discharge cells. In such a falling interval Rd of the ramp waveform R, a wall charge amount within the cell is reduced by the dark discharges and a final wall charge amount is uniformed between all the discharge cells.
Meanwhile, since the ramp waveform R causes a dark discharge at the discharge cell, a weak light is generated in the initialization period. Accordingly, a quantity of light generated in the initialization period is reduced to improve a contrast of the PDP.
FIG. 6 shows a circuit diagram of a ramp waveform generating device.
Referring to FIG. 6, a conventional ramp waveform generating device includes a rising ramp waveform generating device part 40 and a falling ramp waveform generating device part 42.
The rising ramp waveform generating device 40 includes a first switching device M1 provided between a ramp waveform voltage source Vcc and a first electrode Y, a first capacitor C1 provided between a gate electrode of the first switching device M1 and the ramp waveform voltage source Vcc, and a first variable resisting device VR1 provided between the gate electrode of the first switching device M1 and a first ramp control signal generating device 44.
Diodes D2, D3 and D4 for preventing a backward current and resisting devices R3 and R5 for protecting these diodes are provided between the gate electrode of the first switching device M1 and the first ramp control signal generating device 44. A fourth resisting device R4 is arranged between the first variable resisting device VR1 and the first ramp control signal generating device 44. This resisting device R4 is provided to reduce a varying range of the first variable resisting device VR1. A first diode D1 and a first resisting device R1 are connected, in parallel, between the first capacitor C1 and the ramp waveform voltage source Vcc. A second resisting device R2 for protecting the first capacitor C1 is provided between the first diode D1 and the first capacitor C1.
An operation of the rising ramp waveform generating device 40 will be described. First, a ramp control signal generated from the first ramp control signal generating device 44 is applied, via the fourth resisting device R4 and the first variable resisting device VR1, to the first switching device M1. At this time, the ramp control signal applied to the first switching device M1 has a slope resulting from resistance values of the first variable resisting device VR1 and the fourth resistor R4 and a capacitance of the first capacitor C1. In other words, a voltage applied to the gate electrode rises slowly owing to resistances of the first variable resisting device VR1 and the fourth resisting device R4 and a capacitance of the first capacitor C1. Accordingly, a voltage applied from the ramp waveform voltage source Vcc, via the first switching device M1, to the first electrode Y has a rising slope.
The falling ramp waveform generating device 42 includes a second switching device M2 provided between a ground level source GND and a first electrode Y, a second capacitor C2 provided between a gate electrode and a drain electrode of the second switching device M2, and a second variable resisting device VR2 provided between the gate electrode of the second switching device M2 and a second ramp control signal generating device 46.
A fifth diode D5 for controlling a current flow is provided between the gate electrode of the second switching device M2 and the second ramp control signal generating device 46. A sixth resisting device R6 for protecting the fifth diode D5 is provided between the fifth diode D5 and the second ramp control signal generating device 46. A ninth resisting device R9 is arranged between the second variable resisting device VR2 and the second ramp control signal generating device 46. This ninth resisting device R9 is provided to reduce a varying range of the second variable resisting device VR2. A sixth diode D6 and an eighth resisting device R8 are connected, in parallel, between the drain electrode of the second switching device M2 and the second capacitor C2. A seventh resisting device R7 for protecting the second capacitor C2 is provided between the sixth diode D6 and the second capacitor C2.
An operation of the falling ramp waveform generating device 42 will be described. First, a ramp control signal generated from the second ramp control signal generating device 46 is applied to the second switching device M2 after a ramp waveform R in the rising interval Ru was applied to the first electrode Y. Such a ramp control signal is inputted, via the ninth resisting device R9 and the second variable resisting device VR2, to the gate electrode of the second switching device M2. At this time, the ramp control signal applied to the second switching device M2 has a slope resulting from resistance values of the second variable resisting device VR2 and the ninth resisting device R9 and a capacitance of the second capacitor C2. In other words, a voltage applied to the gate electrode rises slowly owing to resistances of the first variable resisting device VR1 and the ninth resisting device R9 and a capacitance of the second capacitor C2. Accordingly, a voltage applied from the first electrode Y, via the second switching device M2, to the ground level source GND has a falling slope.
Such a conventional ramp waveform generating device generates a ramp waveform with the aid of resistances of the switching devices M1 and M2. In other words, a channel range of the drain electrode and the source electrode is controlled to generate a ramp waveform. Accordingly, a lot of heats are generated at the conventional switching devices to cause a damage of the switching devices. Furthermore, a ramp waveform voltage source having a voltage value above 400V should be provided so as to uniformly discharge the discharge cells.